Mandatory educational qualifications and technical domain experience:
• Essential Qualification: M.Tech degree (in VLSI / Microelectronics / Electronics & Communication / allied engineering disciplines) with minimum 7.0 CGPA from a recognized University / Institute.
• Essential Experience: Minimum 1 year of post-qualification hands-on experience in Analog and Mixed Signal Design.
• Desirable Skills: Experience in EDA design tools (Cadence / Synopsys), FPGA implementation, Verilog/VHDL coding, silicon tape-out, and post-silicon IC testing.
Candidates must bring an application letter on plain paper, recent bio-data, and original plus self-attested copies of marksheets, degrees, and experience certificates.
Contractual / RegularSep. 4, 2026
IIEST Shibpur Recruitment 2026 – Walk-in for Project Associate-I (MeitY C2S Chip-to-Startup Project)
Sourced from Official Government PDFVerified Government Notification • Sourced from Official PDF Notification
Sep. 4, 2026Project Associate-I (School of VLSI Technology)
Required Qualification
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Quick Recruitment Snapshot
Key recruitment parameters at a glance before you apply
Vacancies
1 Post (MeitY C2S Project - SoC for Industry 4.0)
Pay Scale
Check Details
Age Limit
Check Details
Job Location
Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 4, 2026
2
Starts
Aug 27, 2026
3
Deadline
Sep 9, 2026
4
Exam Date
Sep 9, 2026
Application Window27 Aug – 9 Sep 2026
Exam / Test Date9 Sep 2026
Eligibility Criteria & Educational Qualifications
Who is eligible to apply for this recruitment? Check essential educational qualifications, branch/stream criteria, and age limits.
Educational Qualification
Age Limit & Relaxations
The maximum age limit is 35 years as on the date of interview (09.09.2026).
• Upper age limit is relaxable up to 5 years for SC, ST, OBC, Women, and Physically Handicapped (PwD) candidates (up to 40 years).
Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
In-Person Registration & Document Verification at School of VLSI Technology
OfflineQualifying Only
Technical Walk-in Interview before the Institute Selection Committee
OfflineMerit Scored
Verification of Original Academic Credentials & Appointment Issuance
OfflineQualifying Only
Selection is conducted through an in-person Walk-in Interview on 09.09.2026 at 11:00 AM at the School of VLSI Technology, Indian Institute of Engineering Science & Technology (IIEST), Shibpur, Howrah - 711103.
• Candidates must bring an application letter on plain paper, recent bio-data, self-attested photocopies of marksheets, certificates, work experience certificate, and valid ID proof.
• Documents will be verified at the time of interview/joining. No TA/DA will be paid for attending the interview.
Evaluation Rubric & Screening Matrix
Verified Official SourceMulti-parameter scoring system used by the evaluation board for candidate screening.
| Evaluation Parameter / Component | Max Marks / Weightage | Assessment Criteria |
|---|---|---|
| M.Tech Academic Credentials & CGPA (Minimum 7.0 Benchmark) | ||
| Hands-on Analog & Mixed Signal Design Experience (OPAMP, Bandgap, Data Converters) | ||
| Technical Viva-Voce on EDA Tools (Cadence/Synopsys), FPGA, Verilog & Tape-out | ||
| SoC Architecture, IoT Hardware Security & Research Motivation |
Aspirant Ground Reality & Career Trajectory
Verified Official SourcePractical service rules, posting locations, transfer policy, and promotion ladder curated from official gazettes.
Work Culture & Environment
Office/fieldwork balance, duties, organizational environment.
Institute of National Importance (INI) campus located along the historic Hooghly River in Shibpur, Howrah. The School of VLSI Technology at IIEST Shibpur is a premier microelectronics center equipped with industry-standard EDA design suites (Cadence Virtuoso, Synopsys, Mentor Graphics) and clean-room testing facilities. The project focuses on System-on-Chip (SoC) design for IoT Industry 4.0 systems incorporating hardware safety and cryptographic primitives under MeitY's national Chip-to-Startup (C2S) programme. Highly collaborative research environment with exposure to multi-project wafer (MPW) silicon tape-out through national foundries (such as SCL Mohali). Excellent stepping stone for registering into the institutional Ph.D. program or transitioning into core semiconductor product companies.
Posting & Transfer Policy
Initial posting criteria, zone preferences, transfer liability.
Contractual research appointment for 2 years (or till project completion) stationed at School of VLSI Technology, IIEST Shibpur, Howrah, West Bengal.
Career & Promotion Ladder
Promotion timeline, seniority ladder, pay grade scaling.
Project Associate-I (₹30,000/- p.m., Years 1–2) -> Institutional Ph.D. Registration -> Senior Project Associate -> Transition to Silicon Design Engineer / Analog Layout Engineer in semiconductor MNCs (Intel, Qualcomm, Texas Instruments, AMD) or academic faculty positions in premier engineering colleges.
Crucial Application Warnings & Eligibility Traps
Avoid common application rejection triggers, photo/signature guidelines, and certificate validity windows.
- Strict In-Person Walk-in Requirement: Selection is conducted via in-person walk-in interview on 09.09.2026 at 11:00 AM at School of VLSI Technology, IIEST Shibpur. No online/remote interview requests will be accommodated.
- Mandatory 7.0 CGPA & 1-Year Analog Experience: Candidates must satisfy both minimum 7.0 CGPA in M.Tech and at least 1 year of post-qualification experience in Analog and Mixed Signal Design.
- Physical Document Verification: Candidates must bring all original educational and experience certificates along with self-attested hard copies and valid ID proof for verification at the time of interview.
- No Travel Allowance: No TA or DA will be paid by the Institute for attending the walk-in interview.
Category-Wise Vacancy Breakdown & Pay Scale
Detailed post distribution across UR, OBC, EWS, SC, ST quotas and 7th CPC Pay Matrix / Monthly Stipend.
Category-Wise Vacancy Distribution
- Open / Unreserved (School of VLSI Technology - MeitY C2S Project)1
Total Vacancies1 Post (MeitY C2S Project - SoC for Industry 4.0)
Pay Scale & Monthly Remuneration
Selected Project Associate-I receives a consolidated remuneration of INR 30,000/- per month.
Initial appointment is for a period of 2 years or until project completion, subject to satisfactory yearly performance evaluation.
Fixed monthly consolidated remuneration of INR 30,000/- under the Chip to Startup (C2S) Programme sponsored by MeitY, Government of India.
How to Apply Online Step-by-Step?
Follow this verified step-by-step application procedure on the official recruitment portal.
Application Fee & Category Concessions
Nil. No application fee is required.
Official Notification & Portal Verification
Direct links to the authorized government portal, official notification PDF, and career portal.
Verified Official Domain
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Similar M.Tech Opportunities
Jobs by Qualifications & States
Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 4, 2026
2
Starts
Aug 27, 2026
3
Deadline
Sep 9, 2026
4
Exam Date
Sep 9, 2026
Application Window27 Aug – 9 Sep 2026
Exam / Test Date9 Sep 2026
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Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
In-Person Registration & Document Verification at School of VLSI Technology
OfflineQualifying Only
Technical Walk-in Interview before the Institute Selection Committee
OfflineMerit Scored
Verification of Original Academic Credentials & Appointment Issuance
OfflineQualifying Only
Selection is conducted through an in-person Walk-in Interview on 09.09.2026 at 11:00 AM at the School of VLSI Technology, Indian Institute of Engineering Science & Technology (IIEST), Shibpur, Howrah - 711103.
• Candidates must bring an application letter on plain paper, recent bio-data, self-attested photocopies of marksheets, certificates, work experience certificate, and valid ID proof.
• Documents will be verified at the time of interview/joining. No TA/DA will be paid for attending the interview.
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Candidates must hold an M.Tech degree in VLSI / Microelectronics / Electronics with at least 7.0 CGPA and possess a minimum of 1 year of hands-on experience in Analog and Mixed Signal Design.
Sarkari Job Khojo is an independent information service and job discovery platform. All recruitment insights, syllabi, previous year exam cutoffs, and selection stages are compiled from official government notifications, gazettes, and recruitment portals. We are not affiliated with, authorized by, or an official representative of any government agency or recruitment board. Always verify details in the official advertisement PDF before applying.