Maulana Abul Kalam Azad University of Technology, West Bengal
Contractual / Regular

MAKAUT Project Associate Recruitment 2026

Sourced from Official Government PDF
Sep. 26, 2026
Project Associate - I

Required Qualification

B.Tech177
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Quick Recruitment Snapshot

Key recruitment parameters at a glance before you apply

Vacancies
2 Posts
Pay Scale
₹25,000 - ₹31,000 per month (+ HRA)
Age Limit
Up to 35 Years
Job Location
West Bengal28Nadia5+1 More...

Crucial Recruitment Dates

Official schedule & key deadlines

Published

Sep 25, 2026

2

Starts

Sep 25, 2026

3

Deadline

Oct 11, 2026

4

Exam Date

TBA

Application Window25 Sep – 11 Oct 2026
Exam / Test DateTo Be Announced

Eligibility Criteria & Educational Qualifications

Who is eligible to apply for this recruitment? Check essential educational qualifications, branch/stream criteria, and age limits.

Educational Qualification

B.E./B.Tech. in Electronics & Communication Engineering / Microelectronics & VLSI Technology / Embedded System / VLSI Design / Electrical Engineering (EE) / Applied Electronics & Instrumentation Engineering (AEIE) / Computer Science & Engineering (CSE) / Electrical & Electronics Engineering (EEE) / Information Technology (IT) with at least 60% marks or CGPA of 6.75 and above.
Desirable: Knowledge of EDA tools, Chip Design, Linux environment, and VLSI design principles.

Age Limit & Relaxations

Upper age limit is 35 years as on the application deadline. Age relaxation applies as per Government of India / MeitY norms for reserved categories.

Check Your Age Eligibility

Selection Procedure & Screening Stages

Verified Official Source

Multi-stage interview and rubric-based evaluation procedure.

Application Scrutiny & Academic Shortlisting

OnlineQualifying Only

Personal Interview & Technical Assessment

OfflineMerit Scored

Selection is based on scrutiny of academic qualifications (B.Tech marks, GATE/NET score, and EDA/VLSI expertise), followed by an interview of shortlisted candidates before the Project Selection Committee. The interview date and time will be intimated to shortlisted candidates via email.

Selection Criteria & Marking Scheme

Verified Official Source

Official weightage breakdown, qualification scoring, and interview evaluation criteria.

Evaluation Parameter / ComponentMax Marks / WeightageAssessment Criteria & Guidelines
Academic Record (B.E./B.Tech CGPA / Marks)40 MarksEvaluation of undergraduate performance in electronics/computer engineering disciplines
GATE / NET Score & Technical Merit20 MarksWeightage for qualifying CSIR-UGC NET or GATE in EC/EE/CS
Hands-on Knowledge in EDA Tools / VLSI Design / Linux20 MarksFamiliarity with EDA simulation, Cadence/Synopsys tools, and Linux scripting
Personal Interview & Research Aptitude20 MarksOral technical interview and suitability assessment before the Project Selection Committee

Aspirant Ground Reality & Career Trajectory

Verified Official Source

Practical service rules, posting locations, transfer policy, and promotion ladder curated from official gazettes.

Work Culture & Environment

Office/fieldwork balance, duties, organizational environment.

Cutting-edge semiconductor chip design research under the Ministry of Electronics & IT (MeitY) C2S (Chips to Startup) initiative in the Department of Microelectronics and VLSI Technology at MAKAUT Haringhata campus. Associates work on 'Analog Digital Mix Signal Processor' architecture, performing IC schematic simulation, layout design, verification using Cadence/Synopsys/Mentor EDA suites on Linux workstations, and silicon tapeout testing. Lab schedule follows university hours (approx. 09:30 AM to 05:30 PM, Monday to Friday) with project milestone-driven deliverables.

Posting & Transfer Policy

Initial posting criteria, zone preferences, transfer liability.

Contractual appointment initially for 1 year or until the end of the financial year, extendable annually based on performance evaluation up to the completion of the project (February 2027). Experience in MeitY C2S projects provides an exceptional gateway for Ph.D. admissions at IITs/IISc or core VLSI R&D roles in semiconductor design MNCs.

Career & Promotion Ladder

Promotion timeline, seniority ladder, pay grade scaling.

Project associates can be considered for progression to Senior Project Associate upon completing requisite research experience and publications, or enroll in sponsored institutional Ph.D. programs subject to university research committee guidelines.
Crucial Application Warnings & Eligibility Traps

Avoid common application rejection triggers, photo/signature guidelines, and certificate validity windows.

  • Dual submission is strictly mandatory: candidates must email their filled application PDF to [email protected] AND complete the online Google Form (https://forms.gle/SdalCCwczaGfwLV5A) before 11 October 2026.
  • Candidates must hold at least 60% marks or 6.75 CGPA in their qualifying B.E./B.Tech degree; applications with lower marks will be screened out.
  • Shortlisting alerts and interview call letters will be dispatched solely via email; candidates must verify their email address and monitor inboxes regularly.
  • No TA/DA will be disbursed for attending the personal interview or joining the position.

Category-Wise Vacancy Breakdown & Pay Scale

Detailed post distribution across UR, OBC, EWS, SC, ST quotas and 7th CPC Pay Matrix / Monthly Stipend.

Category-Wise Vacancy Distribution

  • Project Associate - I (MeitY C2S Project)2
Total Vacancies2 Posts

Pay Scale & Monthly Remuneration

• ₹31,000/- + HRA: For scholars selected through CSIR-UGC NET/GATE or central agency national tests.
• ₹25,000/- + HRA: For candidates without NET/GATE.

Monthly consolidated fellowship: ₹31,000/- + HRA (as per University norms) for candidates with CSIR-UGC NET/GATE; ₹25,000/- + HRA for candidates without NET/GATE.

How to Apply Online Step-by-Step?

Follow this verified step-by-step application procedure on the official recruitment portal.

Application Procedure

  1. Download and print the official application form proforma attached to the notification circular.
  2. Fill out the application form legibly with personal details, educational qualifications, GATE/NET score, and experience details.
  3. Prepare a scanned PDF of the completed form along with self-attested copies of 10th, 12th, B.Tech/degree marksheets, GATE/NET scorecard, age proof, and CV.
  4. Email the consolidated PDF application to [email protected] on or before 11 October 2026.
  5. Also fill out the mandatory Google Form at: https://forms.gle/SdalCCwczaGfwLV5A before the closing date.

Application Fee & Category Concessions

Nil (No application fee required).

Official Notification & Portal Verification

Direct links to the authorized government portal, official notification PDF, and career portal.

Verified Official Domain
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Frequently Asked Questions & Crucial Aspirant Queries

5 Queries Resolved

Clear, verified answers to top eligibility, exam format, salary calculation, and application queries for this notification.

The last date to submit the application via email and fill out the Google Form is 11 October 2026.

Sarkari Job Khojo is an independent information service and job discovery platform. All recruitment insights, syllabi, previous year exam cutoffs, and selection stages are compiled from official government notifications, gazettes, and recruitment portals. We are not affiliated with, authorized by, or an official representative of any government agency or recruitment board. Always verify details in the official advertisement PDF before applying.

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