B.E./B.Tech in Electronics / Instrumentation / ECE from a recognized University or Institute with a good academic record, and must have completed at least one course in VLSI Design or Microelectronics. Desirable: Knowledge of RTL, FPGA, Analog Circuit, Layout Design, Linux commands, and EDA tool installation.
Contractual / RegularSep. 11, 2026
NIT Silchar Recruitment 2026 – Apply for Project Associate-I Post
Sourced from Official Government PDFVerified Government Notification • Sourced from Official PDF Notification
Sep. 11, 2026Project Associate-I
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Quick Recruitment Snapshot
Key recruitment parameters at a glance before you apply
Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 7, 2026
2
Starts
Sep 7, 2026
3
Deadline
Sep 25, 2026
4
Exam Date
TBA
Application Window7 – 25 Sep 2026
Exam / Test DateTo Be Announced
Eligibility Criteria & Educational Qualifications
Who is eligible to apply for this recruitment? Check essential educational qualifications, branch/stream criteria, and age limits.
Educational Qualification
Age Limit & Relaxations
Maximum 35 years as on the closing date of application (25.09.2026). Relaxation on qualification and age for SC/ST/OBC/WOMEN/PWD candidates as per Government of India Rules.
Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
Application Screening & Shortlisting
Document Scrutiny (CV, B.Tech Academic Record, VLSI Coursework)Qualifying Only
Personal Interview
Online / Offline (Department of ECE, NIT Silchar)Merit Scored
Selection will be conducted through initial screening of submitted soft-copy applications and CVs based on B.E./B.Tech academic record and VLSI/Microelectronics coursework. The Institute reserves the discretion to restrict the number of shortlisted candidates. Shortlisted candidates will be notified of the interview date, time, and mode (online or offline) via email. No TA/DA is admissible for attending the interview.
Selection Criteria & Marking Scheme
Verified Official SourceOfficial weightage breakdown, qualification scoring, and interview evaluation criteria.
| Evaluation Area / Component | Assessment Criteria & Guidelines |
|---|---|
| B.Tech Academic Credentials & VLSI Coursework | Performance in B.E./B.Tech in Electronics, Instrumentation, or ECE, including specific coursework and grades in VLSI Design or Microelectronics. |
| RTL, FPGA & Hardware Design Skills | Practical knowledge of Register-Transfer Level (RTL) coding in Verilog/VHDL, FPGA implementation, and analog circuit layout design. |
| EDA Tools & Linux Environment Competency | Familiarity with EDA design software installation, CAD workflows, simulation environments, and standard Linux operating system commands. |
| Interview Technical Rigor & Project Domain Readiness | Technical interview performance evaluating understanding of EEG signal processing, low-power hardware design, seizure detection algorithms, and communication skills. |
Aspirant Ground Reality & Career Trajectory
Verified Official SourcePractical service rules, posting locations, transfer policy, and promotion ladder curated from official gazettes.
Work Culture & Environment
Office/fieldwork balance, duties, organizational environment.
The position is based in the Department of Electronics and Communication Engineering at the National Institute of Technology (NIT) Silchar, an Institute of National Importance under the Ministry of Education. The researcher works on a prestigious Ministry of Electronics and Information Technology (MeitY) sponsored R&D project titled 'Design and Development of Low Power Low Latency Non-Invasive Seizure Detector System' under the leadership of Dr. Koushik Guha and Prof. K.L. Baishnab. Laboratory activities focus on cutting-edge low-power VLSI design, brain-machine interface hardware, biomedical signal processing of EEG datasets, and FPGA prototyping. The research atmosphere is academically rigorous and collaborative, with access to advanced EDA software suites (Cadence, Synopsys, Mentor Graphics) and state-of-the-art semiconductor modeling equipment.
Posting & Transfer Policy
Initial posting criteria, zone preferences, transfer liability.
The engagement is purely temporary and contractual for an initial duration of one year, extendable until the completion of the project (whichever is earlier). The appointment is coterminous with the project and confers no claim, right, or expectation for permanent absorption or regular appointment at NIT Silchar. Selected candidates must sign an agreement at the time of joining.
Career & Promotion Ladder
Promotion timeline, seniority ladder, pay grade scaling.
As a sponsored project role, there is no institutional promotion ladder. However, serving as Project Associate-I under a MeitY project at NIT Silchar provides strong research credentials, paper publication opportunities in IEEE/Springer journals, and serves as an exceptional launchpad for securing direct Ph.D. admissions at top-tier institutions (IITs, IISc, NITs) or research scientist roles in semiconductor multinational companies.
Crucial Application Warnings & Eligibility Traps
Avoid common application rejection triggers, photo/signature guidelines, and certificate validity windows.
- Strict Email Subject Line: Applications must be sent via email with the exact subject line 'Application for the post of Project Associate-I under MeitY project EE-9/2/2021- R&D-E'; deviations may result in filtering out during screening.
- Dual Recipient Requirement: Applications must be emailed to both Principal Investigators ([email protected] and [email protected]) along with the filled Annexure application format, CV, and supporting documents by 25.09.2026.
- Coursework Prerequisite: Candidates must have completed at least one formal course in VLSI Design or Microelectronics during their B.E./B.Tech degree.
- No Objection Certificate (NOC): Employed candidates must produce a valid No Objection Certificate from their current employer at the time of interview.
Category-Wise Vacancy Breakdown & Pay Scale
Detailed post distribution across UR, OBC, EWS, SC, ST quotas and 7th CPC Pay Matrix / Monthly Stipend.
Category-Wise Vacancy Distribution
- Unreserved / Total1
Total Vacancies1
Pay Scale & Monthly Remuneration
Consolidated remuneration of Rs. 31,000/- per month. Candidate will be eligible for HRA as per Project/Institute norms.
Rs. 31,000/- per month + HRA as per Project / Institute norms.
How to Apply Online Step-by-Step?
Follow this verified step-by-step application procedure on the official recruitment portal.
Application Procedure
- Download and fill out the prescribed application format (Annexure 01(A) - 2) from the official recruitment circular.
- Prepare an updated Curriculum Vitae (CV) and scan all supporting documents (degree certificates, marksheets, proof of date of birth, category/caste certificate if applicable, NET/GATE score cards).
- Email the soft copy of the completed application form, CV, and supporting documents to the Principal Investigators at [email protected] and [email protected].
- Format the email subject line strictly as:
Application for the post of Project Associate-I under MeitY project EE-9/2/2021- R&D-E. - Ensure the application email is sent on or before 25th September 2026.
Application Fee & Category Concessions
No application fee is required.
Official Notification & Portal Verification
Direct links to the authorized government portal, official notification PDF, and career portal.
Verified Official Domain
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Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 7, 2026
2
Starts
Sep 7, 2026
3
Deadline
Sep 25, 2026
4
Exam Date
TBA
Application Window7 – 25 Sep 2026
Exam / Test DateTo Be Announced
Latest from National Institute of Technology, Silchar
Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
Application Screening & Shortlisting
Document Scrutiny (CV, B.Tech Academic Record, VLSI Coursework)Qualifying Only
Personal Interview
Online / Offline (Department of ECE, NIT Silchar)Merit Scored
Selection will be conducted through initial screening of submitted soft-copy applications and CVs based on B.E./B.Tech academic record and VLSI/Microelectronics coursework. The Institute reserves the discretion to restrict the number of shortlisted candidates. Shortlisted candidates will be notified of the interview date, time, and mode (online or offline) via email. No TA/DA is admissible for attending the interview.
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Candidates must possess a B.E. or B.Tech degree in Electronics, Instrumentation, or ECE from a recognized University or Institute with a good academic record, including completion of at least one course in VLSI Design or Microelectronics.
Sarkari Job Khojo is an independent information service and job discovery platform. All recruitment insights, syllabi, previous year exam cutoffs, and selection stages are compiled from official government notifications, gazettes, and recruitment portals. We are not affiliated with, authorized by, or an official representative of any government agency or recruitment board. Always verify details in the official advertisement PDF before applying.