Project Scientist: 1st Class B.Tech in CSE/IT/EE or related disciplines with strong background in hardware, computer architecture, and CPU simulators.
Senior Project Scientist: 1st Class M.Tech/MS(R) or 1st Class B.Tech with at least 3 years of relevant experience in CSE/IT/EE or allied areas.
Principal Project Scientist: Ph.D. or 1st Class M.Tech/MS(R) in CSE/IT/EE or related areas with minimum 6 years of post-qualification experience.
Contractual / RegularSep. 10, 2026
IIT Delhi Recruitment 2026 – Apply for 3 Project Scientist Posts
Sourced from Official Government PDFVerified Government Notification • Sourced from Official PDF Notification
Sep. 10, 2026Principal Project ScientistSenior Project ScientistProject Scientist
★
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Quick Recruitment Snapshot
Key recruitment parameters at a glance before you apply
Vacancies
3 Posts
Pay Scale
₹47,790 - ₹83,840/- PM + 27% HRA
Age Limit
As per IIT Delhi IRD rules (Relaxations as per GoI norms)
Job Location
Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 8, 2026
2
Starts
Sep 8, 2026
3
Deadline
Sep 21, 2026
4
Exam Date
TBA
Application Window8 – 21 Sep 2026
Exam / Test DateTo Be Announced
Eligibility Criteria & Educational Qualifications
Who is eligible to apply for this recruitment? Check essential educational qualifications, branch/stream criteria, and age limits.
Educational Qualification
Age Limit & Relaxations
Age limits and relaxations for SC/ST/OBC/PH candidates are applicable in accordance with Government of India and IIT Delhi IRD guidelines. Candidates with specialized experience in chiplet architectures are preferred.
Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
Application Screening & Shortlisting based on Qualifications and Experience
OnlineQualifying Only
Personal Interview before the Selection Committee
OnlineMerit Scored
Applications submitted on prescribed Form No. IRD/REC-4 will be scrutinized by the Department Selection Committee. Shortlisted candidates satisfying advertised qualifications and experience in chiplet architectures/CPU simulation will be informed via email and called for an online test and/or personal interview. The Selection Committee reserves the right to downgrade posts if suitable candidates for higher grades are not found.
Selection Criteria & Marking Scheme
Verified Official SourceOfficial weightage breakdown, qualification scoring, and interview evaluation criteria.
| Evaluation Area / Component | Assessment Criteria & Guidelines |
|---|---|
| Academic & Research Qualifications | 1st Class B.Tech / M.Tech / Ph.D. in Computer Science, Information Technology, or Electrical/Electronics Engineering |
| Domain Experience & Technical Expertise | Demonstrated expertise in Computer Architecture, System-on-Chip (SoC), Chiplet interconnect communication protocols, and Network-on-Chip (NoC) |
| Simulation & Hardware Modeling Tools | Hands-on proficiency in CPU simulators (gem5, Sniper, Multi2Sim, SystemC) and hardware modeling frameworks |
| Interview & Problem-Solving Assessment | Technical depth in multicore communication strategies, cache coherency, latency optimization, and research project feasibility |
Aspirant Ground Reality & Career Trajectory
Verified Official SourcePractical service rules, posting locations, transfer policy, and promotion ladder curated from official gazettes.
Work Culture & Environment
Office/fieldwork balance, duties, organizational environment.
Project appointments under the Industrial Research & Development (IRD) Unit at IIT Delhi in the Department of Computer Science & Engineering provide world-class cutting-edge research exposure. Working on industry-sponsored projects like BAYA Semiconductor's chiplet communication exploration involves intense technical modeling, hands-on simulation using CPU/NoC simulators (gem5, Sniper, SystemC), and close collaboration with premier faculty and semiconductor industry leaders.
Posting & Transfer Policy
Initial posting criteria, zone preferences, transfer liability.
The positions are based at the IIT Delhi main campus in Hauz Khas, New Delhi. Appointments are purely contractual and co-terminus with the project, which is scheduled up to 03 June 2029. Continued appointment is subject to annual performance appraisal and project funding availability.
Career & Promotion Ladder
Promotion timeline, seniority ladder, pay grade scaling.
These are sponsored project positions and do not lead to regular absorption or permanent faculty/cadre appointments at IIT Delhi. However, experience as a Project Scientist at IIT Delhi carries tremendous prestige for future doctoral admissions, post-doctoral opportunities, and core R&D semiconductor engineering roles at top global chip design firms.
Crucial Application Warnings & Eligibility Traps
Avoid common application rejection triggers, photo/signature guidelines, and certificate validity windows.
- Application must be submitted strictly in prescribed Form No. IRD/REC-4 via email to [email protected] on or before 21st September 2026, 5:00 PM; incomplete applications or different formats will be rejected.
- The subject line of the submission email MUST clearly state 'Advertisement No. IITD/IRD/240/2026'.
- The Selection Committee reserves the right to downgrade the advertised posts to lower project positions if suitable candidates for higher grades are not found.
- Appointments are purely contractual, temporary, and co-terminus with the project duration (up to 03 June 2029), with no claim for permanent employment at IIT Delhi.
- Candidates employed in Government, Semi-Government, or Autonomous organizations must produce a No Objection Certificate (NOC) at the time of interview.
Category-Wise Vacancy Breakdown & Pay Scale
Detailed post distribution across UR, OBC, EWS, SC, ST quotas and 7th CPC Pay Matrix / Monthly Stipend.
Category-Wise Vacancy Distribution
- UR3
Total Vacancies3 Posts
Pay Scale & Monthly Remuneration
Principal Project Scientist: ₹64,260 - ₹83,840/- p.m. + 27% HRA.
Senior Project Scientist: ₹60,750 - ₹79,260/- p.m. + 27% HRA.
Project Scientist: ₹47,790 - ₹62,350/- p.m. + 27% HRA.
Consolidated monthly fellowship with annual increments plus 27% HRA under IIT Delhi IRD rules. Sponsoring Agency: BAYA SEMICONDUCTOR INDIA PRIVATE LIMITED (Project No. RM00164N). Posts may be downgraded at the discretion of the Selection Committee if suitable candidates are not found.
How to Apply Online Step-by-Step?
Follow this verified step-by-step application procedure on the official recruitment portal.
Application Procedure
- Download the official application Form No. IRD/REC-4 from the IIT Delhi IRD website (ird.iitd.ac.in).
- Complete the application form with full details of educational qualifications indicating percentage of marks/division of each examination passed, details of work experience, publications, and hardware/architecture project background.
- Attach self-attested scanned copies of educational degrees, mark sheets, experience certificates, and valid photo ID.
- Send the completed application form along with all supporting documents in a single PDF via email to [email protected] with the subject line "Advertisement No. IITD/IRD/240/2026".
- Ensure the email application reaches the Principal Investigator latest by 21st September 2026 up to 5:00 PM.
Application Fee & Category Concessions
No application fee is payable for applying to these project positions.
Official Notification & Portal Verification
Direct links to the authorized government portal, official notification PDF, and career portal.
Verified Official Domain
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Jobs by Qualifications & States
Crucial Recruitment Dates
Official schedule & key deadlines
Published
Sep 8, 2026
2
Starts
Sep 8, 2026
3
Deadline
Sep 21, 2026
4
Exam Date
TBA
Application Window8 – 21 Sep 2026
Exam / Test DateTo Be Announced
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Selection Procedure & Screening Stages
Verified Official SourceMulti-stage interview and rubric-based evaluation procedure.
Application Screening & Shortlisting based on Qualifications and Experience
OnlineQualifying Only
Personal Interview before the Selection Committee
OnlineMerit Scored
Applications submitted on prescribed Form No. IRD/REC-4 will be scrutinized by the Department Selection Committee. Shortlisted candidates satisfying advertised qualifications and experience in chiplet architectures/CPU simulation will be informed via email and called for an online test and/or personal interview. The Selection Committee reserves the right to downgrade posts if suitable candidates for higher grades are not found.
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The deadline to submit the completed application form (Form No. IRD/REC-4) by email to [email protected] is September 21, 2026 up to 5:00 PM.
Sarkari Job Khojo is an independent information service and job discovery platform. All recruitment insights, syllabi, previous year exam cutoffs, and selection stages are compiled from official government notifications, gazettes, and recruitment portals. We are not affiliated with, authorized by, or an official representative of any government agency or recruitment board. Always verify details in the official advertisement PDF before applying.